Samsung to Start Producing Apple's A9 Chips at Austin, TX Plant

[dgstorm]

The latest rumors from both Apple and Samsung have them working hand-in-hand on Apple's A9 internal hardware for the next gen iPhone. According to the intel, the main reason Samsung won the contract with Apple despite the bad blood between the two tech titans, is because Samsung is the only company able to crank out 14nm FinFET technology on a large enough scale to meet Apple's needs.

This new chip design process will supposedly consume 35% less energy yet offer 20% more power than previous Apple chips. The chips will also be 15% smaller than the previous gen 20nm chips.

The other intriguing thing about this news is that these chips supposedly went into production this week in Samsung's Austin, TX plant.

Source: IT

 

[johnomaz]

Hey Samsung, make sure theres a flaw in the chips that allows for easy Jailbreaking =D.

 

[grenefroggie]

LOL!!

Apple would have another reason to sue Samsung. Yay!!!

 

[FoxKat]

14 nanometer fabrication node... Amazing. For reference, a Helium Atom is .1 nanometers. So we're talking about electronic components and board traces (printed wires), being the size of 140 Helium atoms side by side. For further reference, the distance between Silicon atoms of the substrate these components are made on (the "chips"), is only .543 nm, so the 14 nm components are only 26 times larger than the space between the atomic grains of sand (so to speak).

To give some additional reference using inches to represent nanometers think of a 14" beach ball as the component, sitting on a dime used to represent the hole between the silicon atoms (actually a dime is just a bit too large at .705" versus .543", but it's close enough for making the point). There will come a point where the node of manufacture is limited by the space between Silicon atoms. One the node gets too small, the components would actually fall through the Silicon (i.e. the ball would fall through the dime-sized hole).

At some point they will need to find a semiconductor that has a smaller lattice (spaces between atoms). Either that or they'll have to come up with s process to dope (treat or coat), the surface of the Silicon to essentially fill in the holes and make the spaces between atoms smaller. This is essentially what they do to create Gorilla Glass making the surface smoother and less susceptible to scratching.

 

[VirtualCLD]

14 nanometer fabrication node... Amazing. For reference, a Helium Atom is .1 nanometers. So we're talking about electronic components and board traces (printed wires), being the size of 140 Helium atoms side by side. For further reference, the distance between Silicon atoms of the substrate these components are made on (the "chips"), is only .543 nm, so the 14 nm components are only 26 times larger than the space between the atomic grains of sand (so to speak).

To give some additional reference using inches to represent nanometers think of a 14" beach ball sitting on a dime (actually a dime is just a bit too large - .705", but it's close enough for making the point). There will come a point where the node of manufacture is limited by the space between Silicon atoms. One the node gets too small, the components would actually fall through the Silicon (it the ball would fall through the hole).

At some point they will need to find a semiconductor that has a smaller lattice (spaces between atoms). Either that or they'll have to come up with s process to dope (treat or coat), the surface of the Silicon to essentially fill in the holes and make the spaces between atoms smaller. This is essentially what they do to create Gorilla Glass making the surface smoother and less susceptible to scratching.

You are right, and they have been running up against the practical limitations for a while now. That is why the 14nm is FinFET (or trigate or 3D gate) instead of planar bulk CMOS or SOI (Silicon-on-Insulator). However, the process node dimension refers to the minimum channel length of the CMOS transistor only (distance between source and drain). Even then, the actual minimum channel length may be a different size then the process node name. For example, one foundry's 90nm process might have an actual minimum gate length of 100nm instead of 90nm. Or their 65nm process might have a minimum gate length of 60nm, not 65nm.
Also, the wiring tends to be larger than the minimum channel length, so 14nm process node might have a minimum wire width of 25nm.
That being said, the sizes are unbelievably small and it will get harder and harder to go smaller. The International Technology Roadmap for Semiconductors shows process nodes going down to 5nm by ~2020. According to Wikipedia, some experts believe this will be the end of Moore's law (although that has been said many times before).

 

[FoxKat]

Someone who speaks my language!! YAY!

And yes, I agree regarding the minimum channel length versus stated. As in any form of manufacture, the target specification dimensions ("node" in this case), are not a number, but a range between the highest (read smallest), yet previously attained at some point in the past and perhaps the highest, now physically attainable consistently under a new process.

Still, it's incredible to think that we're getting close to the point where even the atoms used to manufacture the components could start falling through the lattice of the semiconductor or bleeding over onto adjacent channels And with 3-dimentional process, gravity is now a bigger factor. I think that by the time we reach 5nm, we'll have moved to another form of computational engine - maybe even not electrical in form, but perhaps light-based such as a holographic processor engine, where light is the catalyst to trigger changes in state of an internal "component", and thereby cause a new data "reflection" which is then used to either amplify, attenuate, or redirect other data, i.e. the transistor switches, etc.

Either that or computational electronics will have moved into a state of suspension where the semiconductor is simply the void or space surrounding the electrons rather than a substrate such as Silicon, sort of like superconductors being used to create a non-conductive insulator around superconductors suspended in a magnetic flux perhaps. Anyway, too deep in thought for 6:00pm, IMHO. LOL!

 

[grenefroggie]

This same issue in terms of the size of components has given Intel quite a few issues in their development of PC processors. It is quite amazing stuff if you understand component electronics. Gone are the days of replacing caps and resistors manually. You need a robot to fix those parts these days.

 

[Ollie]

Dear Apple,

Thank you for choosing us, once again, as your primary go to vendor for your upcoming mobile devices.

In lieu of recent frivolous law suits, by a company we wish to remain un-named, we are disheartened to have to inform you that the cost of our SoCs will have to come at an increase in price to offset patent trolls that have the backing of the United States judiciary system.

The increase in cost will be negligible and will only be put in place until aforementioned lawsuits have been satisfied by our accounting division.

Thank you again for your understanding,

Gregory Lee
President and CEO
Samsung Electronics North America
Samsung Telecommunications America

 

[grenefroggie]

lol!! I love it.